Friday, March 24, 2017

Looking For A Way To Ensure High Signal Quality... | Keysight Community

Looking For A Way To Ensure High Signal Quality... | Keysight Community

Wednesday, March 15, 2017

Helical (Helix) Antenna Design

The helix antenna is a travelling wave antenna, which means the current travels along the antenna and the phase varies continuously. Helix antennas (also commonly called helical antennas) invented by John Kraus give a circular polarized wave.  Helix antennas are referred to as axial-mode helical antennas. The benefits of this helix antenna are it has a wide bandwidth, is easily constructed, has real input impedance, and can produce circularly polarized fields. There are two mode of circular polarization in helix antenna.
Left handed helix antenna: In left handed helix antenna if you curl left hand fingers around the helix, thumb would point up. The waves emitted from this helix antenna are Left Hand Circularly Polarized.
Right handed helix antenna: In right handed helix antenna if you curl right hand fingers around the helix, thumb would point up. The waves emitted from this helix antenna are Right Hand Circularly Polarized
The minimum number of turns for a helix is between 3 and 5. There are many online tools available to calculate design parameter of helical antenna.

Design parameters for Helical Antenna

  • D – Diameter of a turn on the helix antenna.
  • C – Circumference of a turn on the helix antenna (C=pi*D).
  • S – Vertical separation between turns for helical antenna.
  • α  – Pitch angle, which controls how far the helix antenna grows in the z-direction per turn
  • N – Number of turns on the helix antenna.
  • H – Total height of helix antenna, H=NS.

Broad-Band Helix Antenna Design

Below is example of one Helix antenna that work at central frequency 1.35 GHz.
helix1.jpg
Radius-20 mm
Wire Radius – 2 mm
Number of Turn – 12
Height – 400 mm
Rotation- RHS
Helix antennas of at least 3 turns will have close to circular polarization in the +z direction when the circumference C is close to a wavelength.
 helix2.jpg
The helix antenna functions well for pitch angles between 12 and 14 degrees. Typically, the pitch angle is taken as 13 degrees.

Simulated Result

Antenna is simulated using Finite-Difference Time domain (FDTD) technique. Below is simulated return loss and field plot.
helix3.jpg
Helix_gainAntenna radiation pattern ( Far Field data plot) is shown below . Antenna Gain is around 15 dB .
There are many other form of Helix antenna like  quadrifilar helix antenna.The Quadrifilar Helix Antenna has 4 excitations and  each element driven a progressive 90 degrees in phase. Then  Bifilar helix is constructed using two volutes with an equal number of turns, and their starting points positioned 180° apart. The ends of the volutes are connected with a shorting wire which adds to the structural integrity of the antenna.

Helix Antenna Array


Sunday, March 5, 2017

Signal Integrity Analysis of USB 3.0 Data Bus

USB 3.0
USB(Universal Serial Bus) is the most popular connection used to connect a computer to devices such as digital cameras, printers, scanners, and external hard drives. USB is a cross-platform technology that is supported by most of the major operating systems. UART is a computer hardware device that translates data between parallel and serial forms (SerDes). A dual UART (Universal asynchronous receiver/transmitter), or DUART, combines two UARTs into a single chip. The universal asynchronous receiver/transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains a shift register, which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is less costly than parallel transmission through multiple wires. Below is USB 3.0 onboard interconnect and stack of ground and power nets.
USB SI-PI Setup
SERDES is a high-speed serial data link used in integrated circuits (ICs) to serialize the parallel data and transfer it at a much faster rate. A typical SERDES architecture looks like a communication set-up with a transmit and a receive side. At transmit side, a PLL generates the fast clock necessary to drive the serializer. A clock and data recovery (CDR) circuit recovers a clock from the transmitted serial data and retimes the data at the receive side. One advantage of using SERDES is reduced clock skew, so data can be sent at the GHz rate. The main disadvantage in SERDES is timing jitter, the deviation of the actual signal transition from the expected transition in time. Timing skew is not a problem in serial interface because in each data lane, there is only one differential signal in each direction, and there is no external clock signal since clocking information is embedded within the serial signal itself.
usbs2.jpgEM simulated data is extracted for USB data group signals and combined with USB connector EM Data. Simulated result of USB connector to USB controller chip is shown here. This data is combined with other channel components for full channel simulation. From this analysis, important factors from a Signal Integrity point of view (e.g., impedance matching, reflection, attenuation, impedance mismatch, propagating delay, crosstalk, and alignment shapes of connectors) are analyzed.
usbs3
As shown here, without any equalization eye is closed and after applying RX equalization eye is open and meeting USB specification. The idea behind equalization is to use the voltage levels of the other bits to correct the voltage level of the current bit. Due to the inter-symbol interference (ISI) from the frequency dependent loss of the channel, the eye of the received signals is totally closed, and the clock and data cannot be recovered from the severely distorted signals. After the equalizer, the eye of the equalized signals is opened.

Tuesday, February 28, 2017

Printed Conformal Antenna Design

Conformal Antenna

In many applications pertaining to missile, satellite, spacecraft and aircraft a directive antenna mounted on a curved body is required. Conforming the antenna to the surface save space and is often essential for structural reasons. An antenna that conforms to a surface whose shape is determined by considerations other than electromagnetic; for example, aerodynamic or hydrodynamic called conformal Antenna. Microstrip antenna technology is most suitable for conformal applications because of their ability to conform to non-planar structures. Microstrip antenna patches are placed above what may be characterized as a conducting plane with a dielectric substrate separating the patch from the conducting planeThe properties of such an array depend strongly on whether it is small compared to the radius of curvature of the mounting body, in which case it behaves nearly like a planner array or whether it is comparable or large to the radius.
The conformal antenna may be put in the belly of aircraft then there is no need of radome. Besides this, shaping and resolution can be improved by using the conformal antenna as more elements can be accommodated. In conformal antenna, it is found that resonance frequency is same for various curvatures. However, as curvature increases, the pattern broadens.  The aperture design of the conformal array is predicted on the knowledge of the patterns and coupling coefficients in the mutual coupling environment. The analysis and synthesis of the conformal array are slightly more complicated than a linear array with uniform spacing because the array elements point in different directions.
Antenna Design
For the analysis of conformal array antennas, the knowledge of the mutual coupling among the radiating elements and the radiation patterns of individual elements are essential ingredients. The first step in the analysis of conformal antennas is to find the electromagnetic field on the surface or in space in the presence of an arbitrarily shaped body. If the geometry is complex there are several reliable numerical procedures, e.g. the moment method, that is available for solving the radiation problem.
conf2The best way to design conformal antenna is first to design rectangular patch antenna of an array of microstrip patch antenna, then conform this geometry over a curved surface and re-optimize design. As resonant frequency does not change with a curved surface, same dimensions of the patch of the planar surface are modeled over a cylindrical surface. Patch dimensions and width of the feed line are calculated is the same way as of microstrip antenna array. Final optimization is carried out using Electromagnetic CAD software.
conf3.jpgThis is example of one 220-element waveguide-fed microstrip patch array.To reduce the feed loss, a slotted waveguide is used instead of the main feed line to feed the microstrip patch array. To simplify the manufacturing procedure, the slots of the waveguide are etched on the ground plane of the dielectric substrate, and the etched ground plane serves as the upper wall of the waveguide. The cover of this planar array is made of the dielectric substrate and its relative dielectric constant is the same as that of the dielectric substrate under the patch array. The slotted waveguide is excited by a coaxial probe at the center of the bottom wall of the waveguide. The two ends of the waveguide are shorted.
After optimizing rectangular array, this is converted to conformal antenna array as shown below.
conf5.png
conf6.pngSimulated result of this conformal antenna using Finite Time domain Difference ( FDTD) is shown below. The main advantage of this center-fed structure is that it avoids beam squint with frequency. The slotted waveguide is regarded as a linear array, and each waveguide-fed subarray is supposed to be an element of this linear array. If this linear array is end-fed, confessedly, the beam squints with frequency. The center-fed slotted waveguide is equivalent to a two-element linear array, and each array element is an end-fed linear array whose array elements are waveguide-fed subarray.

Friday, February 17, 2017

Time Domain Reflectometry (TDR) Analysis of Transmission Lines

T
ime Domain Reflectometry is the analysis of a conductor lines (interconnects)by sending a pulsed signal into the conductor, and then examining the reflection of that pulse. A TDR transmits a short rise time pulse along the conductor. If the conductor is of a uniform impedance and is properly terminated, the entire transmitted pulse will be absorbed in the far-end termination and no signal will be reflected toward the TDR. Any impedance discontinuities will cause some of the incident signal to be sent back towards the source. By examining the polarity, amplitude, frequencies and other electrical signatures of all reflections; tampering or interconnect discontinuity may be precisely located

Time Domain Reflectometry is the analysis of a conductor lines (interconnects) by sending a pulsed signal into the conductor, and then examining the reflection of that pulse. A TDR transmits a short rise time pulse along the conductor. If the conductor is of a uniform impedance and is properly terminated, the entire transmitted pulse will be absorbed in the far-end termination and no signal will be reflected toward the TDR. Any impedance discontinuities will cause some of the incident signal to be sent back towards the source.
By examining the polarity, amplitude, frequencies and other electrical signatures of all reflections; tampering or interconnect discontinuity may be precisely located.


TDR Analysis Need in Signal Net

TDR : Working Principle

With TDR, step pulse voltage is input into the transmission circuit and the voltage reflected in the transmission circuit is measured over time. The characteristic impedance of the circuit board is then calculated from the voltage drop in the reflected voltage.


TDR Simulation Result of Transmission Line in Smart phone from USB to Chip

TDR Pulse (step waveform) is very important. Rise Time value specifies the rise time of incident TDR pulse. The resolution of a TDR measurement system is directly related to the rise/fall time of the incident pulse. Rise time is specified with either a 10%-90% or a 20%-80% definition.


For example, consider a 20* timestep rise time for a 10%-90% definition, there will be 20 time steps between the time where the waveform has a value of 0.1 to the time it reaches a value of 0.9.


Initial glitch on TDR response Since the instantaneous TDR response is directly calculated from V/I, it reveals the initial glitch on TDR response. It is due to the zero current flowing through at the time = 0

Monday, January 16, 2017

Power of Power Integrity Analysis in High-Speed Digital Designs

Power Integrity Analysis


The Emergence of Power Integrity Analysis

As the speed of the data signal increases, many reasons including power supply noise lead to the degradation of the high-speed signals. In low power high-speed digital interfaces, it is crucial to characterize the whole system power supply in order to minimize power supply noise in the system. High-speed design failures show up as failures at higher operating frequency, data error rates, cross talk errors, and EMI errors. Currently, PI engineers do PI analysis of power system to ensure proper and reliable operation using Electronic Design Automation tools (EDA) before the actual fabrication of board. This reduces board failure chances significantly and also cuts production time.
SI and PI are two distinct but related realms of analysis concerned with the proper operation of digital circuits. In SI, the main concern is to make sure that transmitted 1s looks like 1s at the receiver (and same for the 0s). In PI, the main concern is to ensure that the drivers and receivers are provided with adequate current to send and receive 1s and 0s. SI and PI analyzes concerned with the proper analog operation of digital circuits, therefore; care must be taken at the design stage itself to ensure that the design is in accordance with high-speed design rules.

Power Delivery System

In High-speed digital (HSD) boards there are many power planes. The main focus of Power Integrity Analysis is to find out the PDN complex impedance Z(f) of the complete power system that defines, together with chip current waveform, the voltage variations on-chip power rails. The PDN will act not only as a means of delivering current to ICs, but also as a return current path for signals. A great deal of the crossovers between signals and PI occurs at vias, and for a single-ended signal passing through a via, it is the PDN that acts as the return current path for that signal. To achieve good power integrity, we want the PDN to have the lowest impedance possible. At dc, that means having as low a resistance as possible in the plane shapes. At ac, that means minimizing the impedance between power and ground. That impedance will vary based on where on the board you are—where you place capacitors, how they are mounted, and what type and value of capacitor you use.
In fact, finding that impedance at different locations on the board is often the biggest part of the task in power integrity analysis. Often called decoupling analysis, the goal of this exercise is to find the impedance between power and ground at different locations on the board, usually at the power pins.
This article will highlight the role of simulation in the design of PCB power delivery network (PDN) systems, including the voltage regulator module (VRM), decoupling capacitors (decap), and the spreading parasitic of the power/ground plane. The PDN analysis will focus on both the static case (DC or voltage or IR-Drop) and AC analysis in the frequency domain, with the main focus on PDN impedance. In addition to the AC analysis, I will also demonstrate the decap role to minimize power plane impedance.

Power Integrity (PI) Analysis

In power integrity analysis, the main types of simulations are dc voltage drop analysis, decoupling analysis, and noise analysis. First, dc voltage drop analysis involves the analysis of complex trace and plane shapes on the PCB to determine how much voltage is being lost due to the resistance of the copper. In the PI analysis, energy is distributed through transmission planes that make the analysis more complex than basic SI, since energy is moving in x and y directions, as opposed to just one direction down the transmission line.
pi1

DC Simulation

PI-DC analysis computes the voltage, IR drop (voltage drop), current, and power loss density in the power supply nets. Using this analysis, it is identified how much current is drawn by IC and connector pins or stitching vias at DC operating conditions. Due to excessive voltage drop, the power supply voltage at the IC might fall below the recommended minimum voltage. This can cause malfunctioning of the IC. Excessive current density in the perforated power supply rails can generate excessive heat, which might lead to board failures due to delamination or fusing. Also, excessive current in the stitching vias can lead to failures losing connection. Any number of power supply nets with source and sink models can be simulated together.  The simulated DC IR drop result of 1.8 V VCAUX power plane is shown in Fig. 3. The maximum voltage from VRM to sink (ICs) is 60 mV. Similarly, all PDNs are simulated to get the max voltage drop in power plane.
pi3.png

AC Simulation

At DC, modeling is relatively simple so that the series resistance of traces, plane shapes, and vias need to be calculated. But, for high frequencies, analyzing the impedance between power and ground at various locations on the PDN requires complex calculations. PI-AC analysis computes the impedance for the IC current loads over a broad frequency range. It helps to identify whether the PDN provides a low impedance path from the VRM to the IC. AC analysis is carried out to find out the PDN impedance seen from the IC. The VRMs provides 0.9 V to 5 V, the IC pulls 0.1 to 6 A, and a 5% tolerance on the supply voltage is allowed up to around 300 MHz. The result and target impedance is shown for VCAUX power plane in Fig. 4. Target impedance 0.1 Ω is the green line. At higher frequency, the target impedance specification is more relaxed and rises with frequency. Excessive impedance in a certain frequency range can generate excessive voltage noise, which is also called dynamic IR drop, when the IC power supply pins draw large amounts of transient current required for I/O or core logic switching at rates that fall into that frequency range.
pi4.jpg

Sunday, January 8, 2017

Multilayer Electromagnetic Coupled Microstrip Array Antenna

Multilayer Electromagnetic Coupled Microstrip Array Antenna

The desirable features of antenna for Airborne SAR applications include shaped radiation pattern and wide bandwidth capability, good cross polarization isolation and high power capability. Shaped radiation across the track improves the target dynamic range and compensates the requirement of STC (Sensitivity Time Control) correction at receiver end. Wide bandwidth performance results in finer resolution. Planar array antenna is preferred as compared to reflector type antenna for less air drag.
Proper selection of radiating element for planar array dictates the requirement of large bandwidth, low cross polarization with high gain. Multilayer electromagnetically coupled printed antenna is selected, which overcomes the bandwidth limitation of the conventional Microstrip antenna. Aperture coupled antenna although offers the advantage of optimizing feeder network and patch independently, but the impedance matching is poor due to improper grounding when coaxial feeding below the ground is required for the array.
The complex excitation coefficients for the required shape are computed using null perturbation technique where roots of the polynomial are moved both in radial and angular direction in shaped region and only angular displacement for non-shaped region . The design and development of shaped radiation pattern within 35 degrees with only 8 elements with ripple level better than 0.5 dB is shown here. Eight elements in the linear array also make it possible to design the feeder network for dual polarization with corporate feeding within the limited available inter-element spacing, making the feed network less frequency sensitive. Two linear arrays (8 X 2) are combined at Microstrip feed network level.
Design and Simulations of Microstrip Array
Multilayer printed antenna is selected as the basic radiating element for large bandwidth. In this structure microstrip patch is effectively printed on the foam material whose dielectric constant is nearly equal to air to enhance bandwidth and also to minimize the surface wave propagation. Since patch cannot be printed on the foam material so patch is printed on the opposite face of dielectric sheet and this can be used as radome to protect the antenna against environment. E.M. coupled feeding was selected to avoid the soldering connection to patches and making it more reliable. RT Duroid material 5880 with thickness 0.79 mm is selected for the feeder network to meet the high power requirement. Upper patch dimensions are taken larger than lower patch and is fabricated on RT5880 with h = 0.254 mm and Rohacell foam is introduced with 5 mm height for bandwidth enhancement.
ml5
Linear and planar array design begins with the computation of excitation distribution to be given to each antenna element. Null Perturbation technique was applied to compute the complex excitation distribution with element spacing 41.66 mm.Orchard’s pattern synthesis technique is used here to show that one could obtain a set of excitation distribution resulting in same pattern in elevation plane. For each root that lies off the unit circle, it is possible to have alternate root by keeping the phase angle fixed while the magnitude is inverted.
Feed line network was designed for the distribution and it was optimized using ensemble E.M. simulator for required amplitude and phase with return loss better than –25 dB. Corporate feeding mechanism is preferred for broad bandwidth performance and the gap between the lines are kept minimum 1.2 mm to accommodate feeder network for both the polarization in the limited available inter-element spacing. The feed network was first simulated and optimized by EEsof circuit simulator by modeling asymmetrical coupled line to take into account the effect of the coupling between the lines. This results in less ripples in the shaped patterns because of better phase control of the order of 5 degrees. The same optimized layout was later revalidated by Momentum and minor adjustment in length was carried out for required phase matching.   The performance of the array was simulated taking cynaede easter 1516 adhesive into account.
Simulated return loss performance of the antenna shows required bandwidth. The 2:1 VSWR   bandwidth of the antenna is better than 250 MHz.