As the speed of the data signal increases, many reasons including power supply noise lead to the degradation of the high-speed signals. In low power high-speed digital interfaces, it is crucial to characterize the whole system power supply in order to minimize power supply noise in the system. High-speed design failures show up as failures at higher operating frequency, data error rates, cross talk errors, and EMI errors. Currently, PI engineers do PI analysis of power system to ensure proper and reliable operation using Electronic Design Automation tools (EDA) before the actual fabrication of board. This reduces board failure chances significantly and also cuts production time.
SI and PI are two distinct but related realms of analysis concerned with the proper operation of digital circuits. In SI, the main concern is to make sure that transmitted 1s looks like 1s at the receiver (and same for the 0s). In PI, the main concern is to ensure that the drivers and receivers are provided with adequate current to send and receive 1s and 0s. SI and PI analyzes concerned with the proper analog operation of digital circuits, therefore; care must be taken at the design stage itself to ensure that the design is in accordance with high-speed design rules.
Power Delivery System
In High-speed digital (HSD) boards there are many power planes. The main focus of Power Integrity Analysis is to find out the PDN complex impedance Z(f) of the complete power system that defines, together with chip current waveform, the voltage variations on-chip power rails. The PDN will act not only as a means of delivering current to ICs, but also as a return current path for signals. A great deal of the crossovers between signals and PI occurs at vias, and for a single-ended signal passing through a via, it is the PDN that acts as the return current path for that signal. To achieve good power integrity, we want the PDN to have the lowest impedance possible. At dc, that means having as low a resistance as possible in the plane shapes. At ac, that means minimizing the impedance between power and ground. That impedance will vary based on where on the board you are—where you place capacitors, how they are mounted, and what type and value of capacitor you use. In fact, finding that impedance at different locations on the board is often the biggest part of the task in power integrity analysis. Often called decoupling analysis, the goal of this exercise is to find the impedance between power and ground at different locations on the board, usually at the power pins.
This article will highlight the role of simulation in the design of PCB power delivery network (PDN) systems, including the voltage regulator module (VRM), decoupling capacitors (decap), and the spreading parasitic of the power/ground plane. The PDN analysis will focus on both the static case (DC or voltage or IR-Drop) and AC analysis in the frequency domain, with the main focus on PDN impedance. In addition to the AC analysis, I will also demonstrate the decap role to minimize power plane impedance.
Power Integrity (PI) Analysis
In power integrity analysis, the main types of simulations are dc voltage drop analysis, decoupling analysis, and noise analysis. First, dc voltage drop analysis involves the analysis of complex trace and plane shapes on the PCB to determine how much voltage is being lost due to the resistance of the copper. In the PI analysis, energy is distributed through transmission planes that make the analysis more complex than basic SI, since energy is moving in x and y directions, as opposed to just one direction down the transmission line.
PI-DC analysis computes the voltage, IR drop (voltage drop), current, and power loss density in the power supply nets. Using this analysis, it is identified how much current is drawn by IC and connector pins or stitching vias at DC operating conditions. Due to excessive voltage drop, the power supply voltage at the IC might fall below the recommended minimum voltage. This can cause malfunctioning of the IC. Excessive current density in the perforated power supply rails can generate excessive heat, which might lead to board failures due to delamination or fusing. Also, excessive current in the stitching vias can lead to failures losing connection. Any number of power supply nets with source and sink models can be simulated together. The simulated DC IR drop result of 1.8 V VCAUX power plane is shown in Fig. 3. The maximum voltage from VRM to sink (ICs) is 60 mV. Similarly, all PDNs are simulated to get the max voltage drop in power plane.
At DC, modeling is relatively simple so that the series resistance of traces, plane shapes, and vias need to be calculated. But, for high frequencies, analyzing the impedance between power and ground at various locations on the PDN requires complex calculations. PI-AC analysis computes the impedance for the IC current loads over a broad frequency range. It helps to identify whether the PDN provides a low impedance path from the VRM to the IC. AC analysis is carried out to find out the PDN impedance seen from the IC. The VRMs provides 0.9 V to 5 V, the IC pulls 0.1 to 6 A, and a 5% tolerance on the supply voltage is allowed up to around 300 MHz. The result and target impedance is shown for VCAUX power plane in Fig. 4. Target impedance 0.1 Ω is the green line. At higher frequency, the target impedance specification is more relaxed and rises with frequency. Excessive impedance in a certain frequency range can generate excessive voltage noise, which is also called dynamic IR drop, when the IC power supply pins draw large amounts of transient current required for I/O or core logic switching at rates that fall into that frequency range.
The desirable features of antenna for Airborne SAR applications include shaped radiation pattern and wide bandwidth capability, good cross polarization isolation and high power capability. Shaped radiation across the track improves the target dynamic range and compensates the requirement of STC (Sensitivity Time Control) correction at receiver end. Wide bandwidth performance results in finer resolution. Planar array antenna is preferred as compared to reflector type antenna for less air drag.
Proper selection of radiating element for planar array dictates the requirement of large bandwidth, low cross polarization with high gain. Multilayer electromagnetically coupled printed antenna is selected, which overcomes the bandwidth limitation of the conventional Microstrip antenna. Aperture coupled antenna although offers the advantage of optimizing feeder network and patch independently, but the impedance matching is poor due to improper grounding when coaxial feeding below the ground is required for the array.
The complex excitation coefficients for the required shape are computed using null perturbation technique where roots of the polynomial are moved both in radial and angular direction in shaped region and only angular displacement for non-shaped region . The design and development of shaped radiation pattern within 35 degrees with only 8 elements with ripple level better than 0.5 dB is shown here. Eight elements in the linear array also make it possible to design the feeder network for dual polarization with corporate feeding within the limited available inter-element spacing, making the feed network less frequency sensitive. Two linear arrays (8 X 2) are combined at Microstrip feed network level.
Design and Simulations of Microstrip Array
Multilayer printed antenna is selected as the basic radiating element for large bandwidth. In this structure microstrip patch is effectively printed on the foam material whose dielectric constant is nearly equal to air to enhance bandwidth and also to minimize the surface wave propagation. Since patch cannot be printed on the foam material so patch is printed on the opposite face of dielectric sheet and this can be used as radome to protect the antenna against environment. E.M. coupled feeding was selected to avoid the soldering connection to patches and making it more reliable. RT Duroid material 5880 with thickness 0.79 mm is selected for the feeder network to meet the high power requirement. Upper patch dimensions are taken larger than lower patch and is fabricated on RT5880 with h = 0.254 mm and Rohacell foam is introduced with 5 mm height for bandwidth enhancement.
Linear and planar array design begins with the computation of excitation distribution to be given to each antenna element. Null Perturbation technique was applied to compute the complex excitation distribution with element spacing 41.66 mm.Orchard’s pattern synthesis technique is used here to show that one could obtain a set of excitation distribution resulting in same pattern in elevation plane. For each root that lies off the unit circle, it is possible to have alternate root by keeping the phase angle fixed while the magnitude is inverted.
Feed line network was designed for the distribution and it was optimized using ensemble E.M. simulator for required amplitude and phase with return loss better than –25 dB. Corporate feeding mechanism is preferred for broad bandwidth performance and the gap between the lines are kept minimum 1.2 mm to accommodate feeder network for both the polarization in the limited available inter-element spacing. The feed network was first simulated and optimized by EEsof circuit simulator by modeling asymmetrical coupled line to take into account the effect of the coupling between the lines. This results in less ripples in the shaped patterns because of better phase control of the order of 5 degrees. The same optimized layout was later revalidated by Momentum and minor adjustment in length was carried out for required phase matching. The performance of the array was simulated taking cynaede easter 1516 adhesive into account.
Simulated return loss performance of the antenna shows required bandwidth. The 2:1 VSWR bandwidth of the antenna is better than 250 MHz.
The answer to this question depends to a great extent on the particular antenna problem that is to be analyzed. There are various antenna simulation tools based on different numerical techniques. Software for antenna design can be selected based on antenna type and size. Choosing the right technique for solving an antenna problem is important, as choosing the wrong one can either result in incorrect results, or results which take excessively long to compute.
Several key EM simulation technologies have emerged over recent years. Out of these, simulation technique the Method of Moments (MoM), Finite Element (FEM) and Finite Difference Time Domain (FDTD) solutions are used almost in all commercial software like Momentum, HFSS, CST, Sonnet, EMPro etc. Although in principal these technologies could be used to solve the same problems there are often good practical reasons why one particular simulator is better suited to solving a particular problem type.
There are many considerations to take into account when assessing the suitability of a particular EM analysis tool for antenna like
How easy is it to create the geometric model?
Does this EM solver suitable for my antenna?
Do you need to be an ‘EM guru’ to run the tools?
The first major consideration is whether antenna geometry is ‘Planar’ in nature or whether it is genuinely ‘3D’. For ‘Planar’ structures, Method-of-Moment (MoM) provides the most efficient simulation method and for that reason generally MoM would be recommended for the analysis of planar antennas. Whilst for true ‘3D’ antenna structures like Horn, Parabolic Dish, and Waveguide Antenna then either FEM or FDTD will usually be more appropriate. Applications better suited to FDTD simulation include the likes of antenna placement on vehicles/aircraft and the analysis of antenna performance in the presence of detailed human body models.
Method of Moments
Numerical techniques based on the method of weighted residuals are called moment methods. EM modelers have come to use the term “moment method” synonymously with “boundary element method”. The boundary element method is a moment method applied to the solution of surface integral equations. Most commercial moment method codes are boundary element codes, however the method of weighted residuals can be applied to differential equations as well as integral equations. In general, moment method techniques do an excellent job of analyzing unbounded radiation problems and they excel at analyzing PEC (perfect electric conductor) configurations and homogeneous dielectrics. They are not well-suited to the analysis of complex inhomogeneous geometries.
Finite Element Method
Finite element techniques require the entire volume of the configuration to be meshed as opposed to surface integral techniques, which only require the surfaces to be meshed. However each mesh element may have completely different material properties from those of neighboring elements. In general, finite element techniques excel at modeling complex inhomogeneous configurations. However, they do not model unbounded radiation problems as effectively as moment method techniques.
Finite Difference Time Domain
Finite difference time domain (FDTD) techniques also require the entire volume to be meshed. Normally, this mesh must be uniform, so that the mesh density is determined by the smallest detail of the configuration. Unlike most finite element and moment method techniques, FDTD techniques work in the time domain. This makes them very well-suited to transient analysis problems. Like the finite element method, FDTD methods are very good at modeling complex inhomogeneous configurations. Also, many FDTD implementations do a better job of modeling unbounded problems than finite element modeling codes. As a result, FDTD techniques are often the method of choice for modeling unbounded complex inhomogeneous geometries.
There are numerous other electromagnetic modeling techniques. Methods such as the Transmission Line Matrix Method (TLM), Generalized Multipole Technique (GMT), and others each have their own set of advantages for particular applications.
What is ESD? Electrostatic discharge(ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field.An Electrostatic Discharge (ESD) strike is a constant threat to device reliability and functionality. Many low-voltage core chips or system ASICs only offer device-level Human-Body Model (HBM) ESD device protection, which doesn’t address the risks of system-level ESD strikes.ESD can occur when an electronic device comes near the human body or when it’s around another device (machine interface contact). A prime example involves connecting together two devices, such as plugging a mobile phone into a laptop. The person’s hand may touch the connecting pins, or if the device is charged up, ESD may occur when mating the connectors.
ESD Damage •Burn Out •Breakdown of insulator •Decrease of lifetime •Software Failure
ESD Protection of an Smart Phone Circuit
Electrostatic discharge (ESD) looms as one of the biggest threats to a mobile phone’s sensitive components. ESD is a sudden high voltage spike caused by charged objects touching, or in close proximity to, each other. Since these voltage spikes typically produce thousands of volts, they may damage sensitive components (e.g., ICs) in the system
The IEC61000-4-2standard defines standard test conditions that electronic equipment should withstand. It assumes that the user will take no precautions to prevent any ESD damage, and it defines a variety of levels that the equipment should withstand.
The typical curve for an electrostatic discharge defined by IEC61000-4-2has a rise time of about 1 ns and a peak current level of around 30A.
Static charge is an unbalanced electrical charge at rest. Typically, it is created by insulator surfaces rubbing together or pulling apart. One surface gains electrons, while the other surface loses electrons. This results in an unbalanced electrical condition known as static charge. When a static charge moves from one surface to another, it becomes ESD. ESD is a miniature lightning bolt of charge that moves between two surfaces that have different potentials. It can occur only when the voltage differential between the two surfaces is sufficiently high to break down the dielectric strength of the medium separating the two surfaces. When a static charge moves, it becomes a current that damages or destroys gate oxide, metallization, and junctions. ESD can occur in any one of four different ways: a charged body can touch an IC, a charged IC can touch a grounded surface, a charged machine can touch an IC, or an electrostatic field can induce a voltage across a dielectric sufficient to break it down.